1. Field of the Invention
The invention relates to a circuit, in particular a memory circuit, comprising an output terminal for outputting an output signal, and to a method for generating an output signal.
2. Description of the Related Art
In present-day computer systems, the interfaces to memory components have to become faster in order to be able to transfer the increasing amount of data to be stored or read out. One important example is DRAM memory components. The latter are fabricated in a very cost-effective technology which can be used to achieve low leakage currents and which has a small number of metal planes. One disadvantage of this technology is that the driver capability of output signals at their output terminals is lower than is customary in other integrated circuits. The small area available means, moreover, that the space available for supply line systems in the integrated memory circuit is also restricted, so that the integrated supply lines can be influenced by interference and noise, as a result of which the driver capability of the integrated memory circuit is further reduced.
Interfaces of present-day DRAM memory circuits are operated with clock cycles of up to 400 MHz or more. This operating frequency is for the most part limited by the noise of the output drivers, where noise is to be understood hereafter to mean all types of disturbances that are superposed on signals. Two main sources of noise at the output drivers are the noise caused by the synchronous switching and a signal storage effect.
Even simple DRAM memory circuits have up to 32 output drivers which can switch simultaneously. The noise on account of the synchronous switching is caused by the different number of output drivers switching simultaneously. If, for example, all the output drivers switch simultaneously from a logic one to a logic zero, this causes a great level fluctuation in the supply network. This leads to a much slower signal level change or level transition than in a case in which only one of the output drivers switches from a logic one to a logic zero. As a result, noise occurs which is dependent on the transferred data and impairs the signal quality.
The signal storage effect also impairs the signal quality. The signal storage effect denotes a different switching speed in a case when a specific logic level is driven during a plurality of clock periods and is switched from said specific level to a different level, and a case when a logic level is driven only for one clock period. If switching to the other level is subsequently effected, the signal change takes place at different speeds depending on the case. In the last-mentioned case, the potential of the signal level cannot have been attained completely during the first level—in contrast to the first-mentioned case—, so that the potential of the subsequent second signal level attains the reference potential earlier and, consequently, the signal change can be carried out faster.
The noise in the supply voltage line leads to considerably vitiated data eyes and thus to a considerably vitiated signal quality.
Hitherto, in the design of integrated memory circuits attention has been given to constructing the supply lines and the output drivers such that they are of the same type as symmetrically as possible and to wiring them in an optimized manner in order to reduce the noise.
However, this does not eliminate the effects described above but merely reduces them.